发明名称 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE MEDIUM
摘要 A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated.
申请公布号 US2011161904(A1) 申请公布日期 2011.06.30
申请号 US20100978307 申请日期 2010.12.23
申请人 RENESAS ELECTRONICS CORPORATION 发明人 KONDOU KEIICHIROU;TSUCHIYA HIROYUKI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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