发明名称 Hybrid Error Correction Code (ECC) For A Processor
摘要 In one embodiment, the present invention includes a method for generating a hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic-Hamming code, includes a first residue code based on the data block and a first parity code based on the data block and a Hamming matrix. Then the generated code along with the data block can be communicated through at least a portion of a datapath of a processor. Other embodiments are described and claimed.
申请公布号 US2011154157(A1) 申请公布日期 2011.06.23
申请号 US20100713623 申请日期 2010.02.26
申请人 NAEIMI HELIA 发明人 NAEIMI HELIA
分类号 H03M13/29;G06F11/10;G06F12/02;H03M13/07;H03M13/19 主分类号 H03M13/29
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