| 摘要 |
A regulator 1 includes a regulation computing section 14 for computing and outputting an operation signal MV[n] to allow a process value PV from a controlled target 2 to agree with a target value SV, and an output limiting section 15 for restricting the operation signal MV[n] from the regulation computing section 14 for output to the controlled target 2. The regulation computing section 14 includes at least a speed-type integration regulating section or a position-type integration regulating section. The output limiting section 15 includes a function for outputting a limit deviation signal ´[n] indicative of the degree of deviation from a predetermined limit. The regulator 1 also includes an over-integration computing section 16 for calculating a previous over-integration signal corresponding to a previous over-integration occurred during a previous control cycle on the basis of the speed-type integration regulating signal delivered by the regulation computing section 14 and the limit deviation signal ´[n]. The regulation computing section 14 includes a function for allowing the previous over-integration signal to eliminate the previous over-integration by correcting an integral stored in itself.
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