MULTI-PORT MEMORY CONTROLLER AND MULTI-PORT CACHE

摘要

PURPOSE: A multi port memory controller and a multi port cache are provided to realize minimum circuit configuration and fast processing speed by grouping and processing transactions inputted through a plurality of ports. CONSTITUTION: A transaction grouping unit(111) groups transactions inputted through ports to a line unit of a single port memory. A transaction sorter(112) decides a process sequence of the transaction group and successively stores the transaction group. A transaction executor(114) reads the transaction group according to the stored sequence and generates location information, a control signal, and offset for processing the transaction group. The transaction executor offers the location information and the control signal to the single port memory, and also offers the offset to the data input/output controller(120).