发明名称 VERIFICATION SUPPORT PROGRAM AND VERIFICATION SUPPORT DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To improve completeness of verification on software or hardware. <P>SOLUTION: A faulty node is designated from a structure 100 expressing a scenario group to ve verified. A node Ne similar to the designated faulty node Nf is detected from the structure 100. Thereafter, a path P on the structure 100, which passes the detected similar node Ne, is searched from a start node Na of the structure 100 to generate a scenario for verifying the occurrence of a fault in the similar node Ne. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011118757(A) 申请公布日期 2011.06.16
申请号 JP20090276767 申请日期 2009.12.04
申请人 FUJITSU LTD 发明人 TAKAYAMA KOICHIRO;MORISAWA KAZUMICHI
分类号 G06F11/28 主分类号 G06F11/28
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