发明名称 |
Developing semiconductor circuit design with conditional flipflops to save power consumption |
摘要 |
This disclosure concerns a semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop by using a computer. The semiconductor circuit design method comprises setting the flip-flop based on circuit information on a semiconductor integrated circuit; obtaining a control signal controlling the flip-flop; calculating a first evaluation value indicating a power consumption and a magnitude of a clock skew time when clock gating is applied to the flip-flop; setting a gated clock structure clock-gating the flip-flop when the first evaluation value is higher than a first threshold; calculating a second evaluation value indicating the power consumption and a magnitude of a cell area when a low power flip-flop lower in power consumption than the flip-flop is applied to the flip-flop; and replacing the flip-flop by the lower power flip-flop when the second evaluation value is higher than a second threshold.
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申请公布号 |
US7962883(B2) |
申请公布日期 |
2011.06.14 |
申请号 |
US20080195574 |
申请日期 |
2008.08.21 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KITAHARA TAKESHI;UTSUMI TETSUAKI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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