SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD

摘要

Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.