发明名称 |
MEMORY CONTROLLER WITH REDUCED POWER CONSUMPTION, MEMORY DEVICE, AND MEMORY SYSTEM |
摘要 |
A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.
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申请公布号 |
US2011126039(A1) |
申请公布日期 |
2011.05.26 |
申请号 |
US20100950028 |
申请日期 |
2010.11.19 |
申请人 |
KIM SI-HONG;JUN YOUNG-HYUN;PARK KWNAG-II |
发明人 |
KIM SI-HONG;JUN YOUNG-HYUN;PARK KWNAG-II |
分类号 |
G06F1/06;G11C7/22 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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