发明名称 Low power synchronous memory command address scheme
摘要 A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.
申请公布号 US7940543(B2) 申请公布日期 2011.05.10
申请号 US20080050950 申请日期 2008.03.19
申请人 NANYA TECHNOLOGY CORP. 发明人 CHANG CHIA-JEN;TRUONG PHAT
分类号 G11C5/00;G11C7/00 主分类号 G11C5/00
代理机构 代理人
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