| 摘要 |
PROBLEM TO BE SOLVED: To design a chip layout for reducing circuit area while reducing problems during manufacturing. SOLUTION: The method of designing a semiconductor integrated circuit includes the steps of: calculating the risk of occurrence of a problem for each place on the semiconductor integrated circuit to be designed, based on the result of process simulation performed using a previously designed layout pattern 204 and physical model 201; and correcting a design standard 203 according to the risk for each place and generating a compaction condition 206 for each place. In the step of generating the compaction condition, the compaction condition 206 severer than the design standard 203 is generated for a dangerous area where the risk is higher than a predetermined value, and the compaction condition 206 obtained by moderating the design standard 203 is generated for a first safe area where the risk is lower than the predetermined value. COPYRIGHT: (C)2011,JPO&INPIT
|
