发明名称 |
VECTOR PROCESSING APPARATUS AND METHOD |
摘要 |
There is provided a vector processing apparatus and method allowing for the parallel processing of a plurality of different instructions while maintaining vector processing architecture. The vector processing apparatus includes an instruction memory storing a multiple instruction group including one or more instructions; an instruction fetch unit reading the multiple instruction group from the instruction memory; and a plurality of instruction processing units each receiving the multiple instruction group through the instruction fetch unit, selecting a single instruction from the multiple instruction group according to a previous arithmetic result, and performing a arithmetic operation.
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申请公布号 |
US2011107063(A1) |
申请公布日期 |
2011.05.05 |
申请号 |
US20100848489 |
申请日期 |
2010.08.02 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
CHUNG MOO KYOUNG;KWON YOUNG SU;KIM KYUNG SU |
分类号 |
G06F9/30;G06F9/302 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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