<p>Computing apparatus (11 ) includes a plurality of processor cores (12) and a cache (10), which is shared by and accessible simultaneously to the plurality of the processor cores. The cache includes a shared memory (16), including multiple block frames of data imported from a level-two (L2) memory (14) in response to requests by the processor cores, and a shared tag table (18), which is separate from the shared memory and includes table entries that correspond to the block frames and contain respective information regarding the data contained in the block frames.</p>
