| 摘要 |
PROBLEM TO BE SOLVED: To reduce read errors while improving read speed. SOLUTION: Memory cells are arranged at intersections between a plurality of first wirings and a plurality of second wirings, the memory cell being configured by connecting a rectifier element and a variable resistance element in series. A control circuit is configured to apply a first voltage to a selected first wiring and apply a second voltage lower than the first voltage to a selected second wiring, so that a predetermined potential difference is applied to a selected memory cell. The control circuit is configured to apply the first voltage to the plurality of first wirings in parallel, to simultaneously read data from the plurality of memory cells. The number of first wirings to be simultaneously applied with the first voltage in the simultaneous read operation can be changed. COPYRIGHT: (C)2011,JPO&INPIT |
