| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor device, the method achieving an optimum layout design. SOLUTION: For example, a plurality of seeds SEDs, which become flip-flops from among the whole semiconductor device (TOP), are uniformly set, and as the first tracing processing, the effective ranges (node NDEs) of the SEDs are each extended in parallel so that the values of objective functions (including difficulty levels of timing convergence or the like) for the respective NDEs may become uniform. Then, as the first merging processing, the SEDs which contact each other are integrated as appropriate to reduce the number of NDEs at an certain rate, and then a total cost including the difficulty level of each NDE and the difficulty level of a circuit remaining in the TOP is computed. Then, the second, the third, ... tracing processing and merging processing are repeated as in the first processing until the total cost is worsened. By this, an adequate divisional unit is determined, and a floor plan, a divisional layout, and the like are conducted on the basis of the divisional unit. COPYRIGHT: (C)2011,JPO&INPIT |
