发明名称 |
Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions |
摘要 |
A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. Each of a number of interconnect level layouts is defined to pattern conductive features within corresponding interconnect levels above the gate electrode level.
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申请公布号 |
US7932544(B2) |
申请公布日期 |
2011.04.26 |
申请号 |
US20090561207 |
申请日期 |
2009.09.16 |
申请人 |
TELA INNOVATIONS, INC. |
发明人 |
BECKER SCOTT T.;SMAYLING MICHAEL C. |
分类号 |
H01L27/10 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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