| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique which allows smooth tracing in a data processor including a plurality of CPUs. SOLUTION: The data processor includes a plurality of CPUs each operated synchronously with CPU clock signals (clki0 and clki1) supplied to them and a debugging circuit (200) allowing debugging of user programs executed on the plurality of CPUs on the basis of a supplied debugging clock signal (clkd). The data processor further includes a clock control circuit 300 which generates the debugging clock signal and CPU clock signals so that f1≥f2 is established wherein f1 is a frequency of debugging clock signal supplied to the debugging circuit and f2 is the highest frequency of CPU clock signals supplied to the plurality of CPUs. COPYRIGHT: (C)2011,JPO&INPIT
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