| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce peak current during a refresh operation in a semiconductor memory device that includes a plurality of core chips and interface chips. <P>SOLUTION: A semiconductor memory includes a plurality of core chips CC0 to CC7 to which chip information LID different from each other is imparted in advance. An internal refresh command REFa is divided into a plurality of refresh commands REFb having different timing from each other. A refresh operation is performed on a core chip in which a count value C2 of the divided refresh command REFb and at least a portion of the chip information LID are matched. With this configuration, even if the internal refresh command REFb is commonly supplied to the plurality of core chips CC0 to CC7, timing for the refresh operation in respective core chips can be shifted. Accordingly, peak current during the refresh operation can be reduced. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
