| 摘要 |
A multi-phase signals generator is disclosed. The multi-phase signals generator mentioned above includes a frequency divider and N delay circuits. The frequency divider receives a clock signal and divides a frequency of the clock signal to generate a divided frequency clock signal. The N delay circuits are connected in series. The delay circuit connected in a first stage receives the divided frequency clock signal. The delay circuit connected in an ith stage receives an output of the delay circuit connected in an (i−1)th stage, wherein i is an integer larger than 2. The delay circuits respectively delay a received signal according to the clock signal and generate N delay output signals, wherein N is an integer larger than 3. Moreover, a plurality of times for transmitting the clock signal to all of the delay circuits are the same.
|
