| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce a junction leak current in a bit line contact of a nonvolatile semiconductor memory, especially a NAND type flash memory, when "1" is set, to reduce power consumption of the chip. <P>SOLUTION: When data is written in a memory cell transistor while stepwise increasing a write voltage on a word line, write inhibition voltage which has two or more values corresponding to values of the write voltage on the word line is applied to a bit line connected to the memory cell transistor to be written, and selection gate line voltage which has two or more values corresponding to the two or more values of the write inhibition voltage applied to the bit line is applied to a selection gate electrode line of the selection gate transistor. Accordingly, reverse bias in the bit line contact is lowered to reduce a leak current in the bit contact, thereby reducing power consumption of the chip. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
