发明名称 IMAGE PROCESSING APPARATUS AND INTERFACE CONTROL METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To eliminate a conventionally required one-line buffer to allow image data to be transmitted by a clock signal and an effective pixel signal showing timing of effective pixels of image data, with respect to an interface using a synchronizing clock, the effective pixel signal, and image data. SOLUTION: An image processing apparatus wherein the clock signal, an image data signal, and the effective pixel signal showing effective pixels of the image data signal are transmitted from a first image processing unit to a second image processing unit, determines whether transmission timing of an image data signal within one line has come(S400) on the basis of the effective pixel signal and the number of effective pixels being output synchronously with the effective pixel signal and, if transmission timing of the image data signal within one line has come, outputs the clock signal of the first processing unit to the second processing unit synchronously with the effective pixel signal (S402) and, unless transmission timing of the image data signal within one line has come, outputs the clock signal of the first processing unit to the second image processing unit (S404). COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011071656(A) 申请公布日期 2011.04.07
申请号 JP20090219762 申请日期 2009.09.24
申请人 CANON INC 发明人 TACHIKAWA TOMOHIRO
分类号 H04N1/028 主分类号 H04N1/028
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