PLD ARCHITECTURE FOR FLEXIBLY ARRANGING IP FUNCTION BLOCK

摘要

PROBLEM TO BE SOLVED: To provide a PLD architecture capable of arranging an IP function block so as to optimize a routing architecture of a base signal.

SOLUTION: A programmable logic device (PLD) has: two or more logic elements (LE) configured into an array; and a routing architecture of a base signal provided with a plurality of signal rooting lines for rooting signals between LEs. A hole is formed in the LE array. The hole is characterized by a peripheral part and a central part. The routing architecture of the base signal is at least partially interrupted in the hole. The PLD further has an interface circuit at the periphery part of the hole. The interface circuit can be configured in such a way that the circuit in the hole is combined with architecture in which signals are subjected to routing. The PLD further has an IP function block in the hole and is electrically connected with the interface circuit.

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