| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a deviation in reset timing between a plurality of circuits and to reduce cost. <P>SOLUTION: The data transfer apparatus includes a clock generation unit 100, a control unit 200, and a plurality of transmission units 300, 400. In order to synchronize clocks in a plurality of modules, each of the plurality of transmission units uses continuous rising edges of a bit clock to sample the reset signal multiple times so that a phase shift of the reset signal between the transmission units can be reduced, and the phase of the frequency dividing clock is aligned in each transmission unit. <P>COPYRIGHT: (C)2011,JPO&INPIT |
