发明名称 INTERLACED ITERATIVE SYSTEM DESIGN FOR 1K-BYTE BLOCK WITH 512-BYTE LDPC CODEWORDS
摘要 To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.
申请公布号 US2011078540(A1) 申请公布日期 2011.03.31
申请号 US20090610094 申请日期 2009.10.30
申请人 STMICROELECTRONICS, INC. 发明人 HU XINDE;PARTHASARATHY SIVAGNANAM;GARANI SHAYAN SRINIVASA;WEATHERS ANTHONY;BARNDT RICHARD
分类号 H03M13/05;G06F11/10;H03M13/27 主分类号 H03M13/05
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