发明名称
摘要 An apparatus generates design information on a via hole that passes through predetermined layers of a multilayer wiring board, by storing information on at least one of a shape and a size of a land to be provided around the via hole. When designing a via hole that passes through a plurality of internal layers of the wiring board, the land information for an internal layer is applied to each internal layer through which the via hole passes.
申请公布号 JP4659549(B2) 申请公布日期 2011.03.30
申请号 JP20050217489 申请日期 2005.07.27
申请人 发明人
分类号 G06F17/50;H05K3/00;H05K3/46 主分类号 G06F17/50
代理机构 代理人
主权项
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