发明名称 |
Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state |
摘要 |
A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.
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申请公布号 |
US7917700(B2) |
申请公布日期 |
2011.03.29 |
申请号 |
US20070924163 |
申请日期 |
2007.10.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
IRISH JOHN DAVID;MCBRIDE CHAD B.;RANDOLPH JACK CHRIS |
分类号 |
G06F12/12 |
主分类号 |
G06F12/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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