发明名称 |
MEMORY CELL EMPLOYING REDUCED VOLTAGE |
摘要 |
A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.
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申请公布号 |
US2011069565(A1) |
申请公布日期 |
2011.03.24 |
申请号 |
US20100957936 |
申请日期 |
2010.12.01 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MIKAN, JR. DONALD GEORGE;MAIR HUGH;HOUSTON THEODORE W.;CLINTON MICHAEL PATRICK |
分类号 |
G11C5/14 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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