| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an image processing circuit in which a mounting area is reduced. <P>SOLUTION: An image processing circuit includes: a first arithmetic unit for determining a first constant to be arithmetically operated from a pixel on a row direction among a plurality of pixels surrounding an interpolation pixel, a second constant to be arithmetically operated from a pixel on a column direction and a third constant to be arithmetically operated from a plurality of pixels; a second arithmetic unit for determining a third weighting factor by arithmetically operating a first weighting factor to be decided from a position of the interpolation pixel relative to the pixels on the row direction and a second weighting factor to be decided from a position of the interpolation pixel relative to the pixel on the column direction; a third arithmetic unit for arithmetically operating a pixel value change amount per first weighting factor in accordance with the first constant; a fourth arithmetic unit for arithmetically operating a pixel value change amount per second weighting factor in accordance with the second constant; a fifth arithmetic unit for arithmetically operating a pixel value change amount per third weighting factor in accordance with the third constant; and a sixth arithmetic unit for arithmetically operating a pixel value of the interpolation pixels on the basis of arithmetic results of the third, the fourth and the fifth arithmetic units. <P>COPYRIGHT: (C)2011,JPO&INPIT |
