发明名称 Parallel Timing Analysis For Place-And-Route Operations
摘要 Signal paths in a circuit design are identified, and each node in each path to be processed by an electronic design automation operation is assigned a value. More particularly, each node in a signal path to be processed is sequentially assigned an incrementing value. If a node occurring in multiple signal paths already has been assigned a value, and the new value to be assigned to the node is higher than its previously-assigned value, then the node is assigned the higher value. Two or more portions of the circuit design having the same assigned node values are then processed in parallel by the electronic design automation operation.
申请公布号 US2011072404(A1) 申请公布日期 2011.03.24
申请号 US20090566652 申请日期 2009.09.24
申请人 SRINIVAS PRASANNA V 发明人 SRINIVAS PRASANNA V.
分类号 G06F17/50 主分类号 G06F17/50
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