MULTIPLE RANDOM ERROR CORRECTING SYSTEM

摘要

1,247,823. Error-correcting systems. INTERNATIONAL BUSINESS MACHINES CORP., and ROBERT TIENWEN CHIEN. 8 Jan., 1970 [8 Jan., 1969], No. 1041/70. Heading G4A. A message containing k data bits has 2m check bits added to it (k#m2, where m=integer greater than 1) for each of t error-correcting capabilities (t#1), and a decoder comprises t parity-checking circuits supplying outputs to an error-correcting circuit for that bit. As an example, where k=25 and m=5, the message bits d 0 -d 24 are considered arranged as a 5 x 5 matrix, check bits c 1 -c 5 are derived by exclusive OR operation on the matrix rows (e.g. c 1 =EXOR (do, d 1 , d 2 , d 3 , d 4 ) and check bits c 6 -c 10 are similarly derived from the matrix columns (e.g. c 6 =EXOR d 0 , d 5 , d 10 , d 15 , d 20 ) to provide for single error correction. For each additional error correction capability, a pair of orthogonal Latin squares such as L 1 , L 2 and L 3 , L 4 , Fig. 4, is used to select two groups of 5 bits from the matrix, each group comprising bits located in positions marked with the same number in the Latin squares, the additional check bits c 11 -c 15 (L 1 ), C 16 -C 20 (L 2 ) again being derived by exclusive OR operation on the 5 selected bits. Each bit d 0 -d 24 therefore occurs in only two of the equations defining each set of mt check bits. For each bit, such as d 0 , the error-correcting decoder comprises a module I-III, Fig. 5, for each error-correcting capability, each module consisting of a pair of exclusive OR circuits such as 30, 32 receiving inputs corresponding to the check bit equations in which that bit occurs, e.g. for do circuit 30 has inputs d 1 -d 4 and c 1 . Each circuit 30, 32 provides an output which should be a copy of the corresponding bit, and these copies, together with the original bit are supplied to a majority logic gate 38 to provide a corrected output, assuming not more than the number of random errors allowed for have occurred. For the ease where k