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发明名称
Herstellungsverfahren für MOS-Transistor mit verringerter Gate-Länge und einen solchen Transistor enthaltener integrierter Schaltkreis
摘要
申请公布号
DE60335930(D1)
申请公布日期
2011.03.17
申请号
DE20036035930
申请日期
2003.05.27
申请人
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIESALTERNATIVES;STMICROELECTRONICS S.A.
发明人
LENOBLE, DAMIEN;GUILMEAU, ISABELLE
分类号
H01L21/336;H01L21/265;H01L29/417
主分类号
H01L21/336
代理机构
代理人
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地址
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