发明名称 Synchronization method and program for a parallel computer
摘要 Barrier synchronization between multiprocessors is performed at high speed while reducing overhead of parallel processing without adding any special hardware mechanism. A parallel computer synchronization method is provided to synchronize threads through barrier synchronization for parallel execution of plural threads on plural processor modules. The parallel computer has plural processor modules (P0 and P1) equipped with plural processor cores (cpu0 to cpu3). The processor cores are each assigned plural threads (Th0 to Th7) to execute multithread processing. The plural threads (Th0 to Th7) are set in hierarchical groups (Gr), and barrier synchronization is performed on each group separately.
申请公布号 US7908604(B2) 申请公布日期 2011.03.15
申请号 US20050312345 申请日期 2005.12.21
申请人 HITACHI, LTD. 发明人 TAKAYAMA KOICHI;AOKI HIDETAKA
分类号 G06F9/46 主分类号 G06F9/46
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