<p>A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal (CLKl) on the IC chip and receiving a second clock signal (CLK2) on the IC chip having a variable delay relative to the first clock signal. A signal (pulse) having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM).</p>
