发明名称
摘要 <P>PROBLEM TO BE SOLVED: To provide a shift register circuit equipped with a plurality of stages of circuit blocks for using the level change of a driving pulse to perform shifting and signal output operations and capable of sequentially outputting external output signals having a stable signal level for the circuit block of each stage, its driving and controlling method, and a driving and controlling device equipped with the shift register circuit. <P>SOLUTION: The shift register circuit is provided with a plurality of stages of signal holding blocks RSA (k) having an input terminal IN and an output terminal OUT sequentially and serially connected thereto, and constructed in such a manner that the output signal of the signal holding block RSA (k) of each stage is taken out as an external output signal GS (k), and supplied as a shift signal to the signal holding block RSA (k+1) of a next stage. Three kinds of control clocks CKA, CKB and CKC having different phases are individually supplied to the signal holding blocks RSA (k) according to the stage numbers. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP4645047(B2) 申请公布日期 2011.03.09
申请号 JP20040062783 申请日期 2004.03.05
申请人 发明人
分类号 G11C19/00;G11C19/28;G09G3/20;G09G3/36;H04N5/335;H04N5/374;H04N5/376 主分类号 G11C19/00
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