发明名称 Integrating a boolean SAT solver into a router
摘要 One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes.
申请公布号 US7904867(B2) 申请公布日期 2011.03.08
申请号 US20070732848 申请日期 2007.04.04
申请人 SYNOPSYS, INC. 发明人 BURCH JERRY R.;DAMIANO ROBERT F.;HO PEI-HSIN;KUKULA JAMES H.
分类号 G06F17/50 主分类号 G06F17/50
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