发明名称 Frequency-locked loop calibration of a phase-locked loop gain
摘要 The present invention relates to a calibrated phase-locked loop (PLL), which has a calibration mode for measuring a tuning gain of a variable frequency oscillator (VFO) and a PLL mode for normal operation. Calibration information based on the tuning gain is used during the PLL mode to regulate a PLL loop gain. During the calibration mode, the calibrated PLL operates as a frequency-locked loop (FLL) for low frequency lock times, and during the PLL mode the calibrated PLL operates as a PLL for high frequency accuracy and low noise. By regulating the PLL loop gain, the desired noise spectrum and dynamic behavior of the PLL may be maintained in spite of variations in the operating characteristics or in the characteristics of the PLL components.
申请公布号 US7898343(B1) 申请公布日期 2011.03.01
申请号 US20080341638 申请日期 2008.12.22
申请人 RF MICRO DEVICES, INC. 发明人 JANESCH STEPHEN T.
分类号 H03L7/00 主分类号 H03L7/00
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