发明名称 |
Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product |
摘要 |
In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log24 is also formed in the LFSR. As a result, a smaller clock count is required for the LFSR to output a test pattern that matches a test pattern automatically generated by an ATPG.
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申请公布号 |
US7895492(B2) |
申请公布日期 |
2011.02.22 |
申请号 |
US20080073553 |
申请日期 |
2008.03.06 |
申请人 |
FUJITSU LIMITED |
发明人 |
HIRAIDE TAKAHISA;MATSUO TATSURU |
分类号 |
G06F11/263;G06F11/30 |
主分类号 |
G06F11/263 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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