| 摘要 |
High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.
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