发明名称 |
Method for Wafer-Level Testing of Integrated Circuits |
摘要 |
A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.
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申请公布号 |
US2011037494(A1) |
申请公布日期 |
2011.02.17 |
申请号 |
US20090539328 |
申请日期 |
2009.08.11 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUNG TSUNG-YANG;WANG AARON |
分类号 |
G01R31/26 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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