发明名称 Power consumption analyzing method and computer-readable storage medium
摘要 A power consumption analyzing method, to be implemented by a computer, is for a circuit developing procedure that makes a logic design of the circuit in an RTL design stage and inserts a gated clock with respect to the circuit in a subsequent logic synthesis stage. The method comprises an extraction step, implemented by the computer, extracting a signal which is judged that it will be transformed into a gated clock in the logic synthesis stage, and storing the signal in a memory part, a measuring step, implemented by the computer, measuring an valid time of the signal stored in the memory part by a logic simulation, and storing the valid time in the memory part, and a post-simulation step, implemented by the computer, computing a power consumption analysis result of the circuit from the valid time stored in the memory part, a number of registers for each of modules that are function units forming the circuit, and a memory capacity coefficient indicating an extent to which a memory capacity within the circuit affects the power consumption of the circuit, and outputting the power consumption analysis result.
申请公布号 US7882458(B2) 申请公布日期 2011.02.01
申请号 US20070907822 申请日期 2007.10.17
申请人 FUJITSU LIMITED 发明人 TAMAKI KAZUHIDE;FUJITA RYUJI;NIITSUMA JUNICHI;SASAKI TAKAYUKI
分类号 G06F17/50 主分类号 G06F17/50
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