发明名称 Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length
摘要 At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.
申请公布号 US7879669(B1) 申请公布日期 2011.02.01
申请号 US20060527265 申请日期 2006.09.25
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 TENG CHIH SIEH;BULUCEA CONSTANTIN;SHYU CHIN-MIIN;WANG FU-CHENG;CHAPARALA PRASAD
分类号 H01L29/78 主分类号 H01L29/78
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