发明名称 Autonomously cycling data processing architecture
摘要 An electronic data processing circuit is disclosed having at least an instruction memory, an instruction decoder; and a slot structure. The slot structure is characterized by a plurality of slots. Each slot has at least: (1) an address register (2) a data register, (4) a function register, and (3) a monitoring circuit. Each slot asynchronously performs operations defined by the information content of their respective address register, data register and function register when complete information is present.
申请公布号 AU9502098(A) 申请公布日期 1999.04.12
申请号 AU19980095020 申请日期 1998.09.23
申请人 THESEUS LOGIC, INC. 发明人 KARL FANT;LARRY KINNEY
分类号 G06F9/34;G06F9/38 主分类号 G06F9/34
代理机构 代理人
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