发明名称 INFORMATION PROCESSING APPARATUS AND MEMORY ACCESS ARBITRATION METHOD
摘要 PROBLEM TO BE SOLVED: To implement a small scale mechanism for inputting/outputting data to/from a memory at high speed having always high priority for a built-in memory of a processor.SOLUTION: An information processing apparatus includes a processor for executing pipeline processing to instructions, a memory built in the processor, and an input/output control means for accessing the memory with high priority. A memory access arbitration method includes the steps of suspending clock supply to the processor when accesses to the memory from the processor and the input/output control means compete (S512), executing the access to the memory from the input/output control means (S506), and releasing the clock wait of the processor after the access to the memory from the input/output control means ends and executing the access to the memory from the processor (S507, S511).
申请公布号 JP2011018355(A) 申请公布日期 2011.01.27
申请号 JP20100192319 申请日期 2010.08.30
申请人 PANASONIC CORP 发明人 MORI ATSUHIRO
分类号 G06F12/00;G06F13/362 主分类号 G06F12/00
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