发明名称 CLOCK GENERATING CIRCUIT, TRANSCEIVER AND RELATED METHOD
摘要 A clock generating circuit includes: a phase detector for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a filter for filtering the control signal to generate a filtered control signal; a controllable oscillator for generating a plurality of output clocks according to the filtered control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; and a feedback circuit for generating the input clock according to the feedback clock.
申请公布号 US2011019716(A1) 申请公布日期 2011.01.27
申请号 US20090649348 申请日期 2009.12.30
申请人 YEN CHIN-HSIEN 发明人 YEN CHIN-HSIEN
分类号 H04B1/69;H03K3/00;H04B1/38 主分类号 H04B1/69
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