发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PROBLEM TO BE SOLVED: To suppress fluctuation in gain characteristics at a voltage controlled oscillator.SOLUTION: The voltage controlled oscillator 11 includes an inductor 100, a fine tuning capacitor 101p, and a rough tuning capacitor 102p, and generates an oscillation clock CKout. A frequency divider 12 divides the oscillation clock CKout to generate a frequency divided clock CKdiv. In the rough tuning mode, a DC voltage supply circuit 13 supplies a DC voltage V13 to a control node Ni and changes the voltage value of the DC voltage V13 according to a DC value of an oscillation voltage VP. In the rough tuning mode, a frequency band selection circuit 14 switches the capacitance value of the rough tuning capacitor 102p so as to set the oscillation frequency band of the voltage controlled oscillator 11 to an oscillation frequency band corresponding to a target frequency based on frequency difference between a reference clock and the frequency divided clock. In the fine adjustment mode, an oscillation control circuit 15 increases or decreases a control voltage VT according to a phase difference between the reference clock and the frequency divided clock.
申请公布号 JP2011009849(A) 申请公布日期 2011.01.13
申请号 JP20090148810 申请日期 2009.06.23
申请人 PANASONIC CORP 发明人 SAWADA AKIHIRO
分类号 H03L7/187;H03L7/099 主分类号 H03L7/187
代理机构 代理人
主权项
地址
您可能感兴趣的专利