| 摘要 |
The present invention utilizes an asynchronous pipeline cycle to facilitate increased average pipeline processing speed. Present invention adjustable cycle pipeline systems and methods minimize “stalls” in execution stages that would otherwise be required to compensate for differences in execution periods. In one embodiment, an adjustable cycle pipeline system includes a fetch stage, a decode stage, an execution stage, and a write stage. The fetch stage fetches information associated with an operation. The decode stage decodes the instructions including determining an instruction execution period. The execution stage executes instructions in accordance with the execution period and the write stage writes the results. In one exemplary implementation the instruction execution period corresponds to a particular number execution sub-clock cycles and the decode stage includes a decode operation timetable for indicating a period of time to complete execution of an operation. The sub-clock controls operations of the execution stage.
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