| 摘要 |
<p>To efficiently manufacture an integrated circuit including an I/O register. On the basis of behavior level design data 851, I/O register access information 852 is generated which includes information on access control from a user logical circuit 313 to an I/O register of an I/O register circuit 312 and specification information on the I/O register. Then, on the basis of the I/O register access information 852 and association of an SW address with an HW address, address map information 853 including association of an SW register on a processor device 350 side with an HW register on the user logical circuit 313 side is generated, the SW address being used when the processor device 350 accesses the I/O register, and the HW address being used when the user logical circuit 313 accesses the I/O register. Thereafter, on the basis of the behavior level design data 851 and the address map information 853, behavior level design data 854 is generated which describes an internal structure of the I/O register circuit 312.</p> |
