发明名称 Cache logic, data processing apparatus including cache logic, and a method of operating cache logic
摘要 Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request. Whilst the eviction is taking place, the control logic allows the current content of the selected cache line to be accessed by subsequent read access requests seeking to read a data value within that current content, but prevents the current content of the selected cache line being accessed by subsequent write access requests seeking to write to a data value within that current content.
申请公布号 US7856532(B2) 申请公布日期 2010.12.21
申请号 US20060592320 申请日期 2006.11.03
申请人 ARM LIMITED 发明人 LATAILLE NORBERT BERNARD EUGENE;AIRAUD CEDRIC DENIS ROBERT;RAPHALEN PHILIPPE JEAN-PIERRE
分类号 G06F13/00 主分类号 G06F13/00
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