| 摘要 |
PURPOSE: A semiconductor memory apparatus and a probe test control circuit therefore are provided to accurately screen the failure of a memory cell due to leakage current in bare chip by selectively activating the word line included in the mat of a certain bank. CONSTITUTION: A bank active circuit(10) generates a bank active signal. A mat active circuit(20) generates the sub-word line selection signal at mats. The mat active circuit supplies the mat sub-word line selection signal to the memory bank. The bank active circuit comprises a latch unit and a bank active controller. The latch unit outputs an address latch signal. The bank active controller outputs a bank active signal.
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