发明名称 ULSI MICRO-INTERCONNECT MEMBER HAVING RUTHENIUM ELECTROPLATING LAYER ON BARRIER LAYER
摘要 An object of the present is to provide a ULSI micro-interconnect member having a seed layer which, particularly on the inner sidewalls of vias and trenches, is formed with a sufficient coverage and a film thickness uniform with that on surface portion, and which has a low level of impurities. Further objects of the invention are to provide a ULSI micro-interconnect member in which, by utilizing such a seed layer to subsequently effect copper electroplating, micro-interconnects have been formed without generating voids; a process for forming the same; and a semiconductor wafer in which such ULSI micro-interconnects have been formed. A ULSI micro-interconnect member having a substrate and a ULSI micro-interconnect formed on the substrate, wherein the ULSI micro-interconnect includes a barrier layer formed on the substrate and a ruthenium electroplating layer formed on the barrier layer; the ULSI micro-interconnect member further including a copper electroplating layer formed using the ruthenium electroplating layer as a seed layer; and a process for fabricating the ULSI micro-interconnect members.
申请公布号 US2010314766(A1) 申请公布日期 2010.12.16
申请号 US20090735187 申请日期 2009.01.08
申请人 SEKIGUCHI JUNNOSUKE;IMORI TORU;KINASE TAKASHI 发明人 SEKIGUCHI JUNNOSUKE;IMORI TORU;KINASE TAKASHI
分类号 H01L23/48;H01L21/4763 主分类号 H01L23/48
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