发明名称 DEVICE FOR MEASURING SETTLING TIME
摘要 PROBLEM TO BE SOLVED: To provide a device for measuring a settling time with high accuracy by sampling a signal to be evaluated. SOLUTION: A controller 101 controls a sampling circuit 103 to sample at a prescribed time synchronized with the cycle of an object signal 107 for evaluation. After the sampling times reach a preset value, or after changes in an output voltage of a hold capacitor reach a prescribed value or lower, the controller resets the sampling time by delaying a prescribed time period, and restarts to sample at the reset time and calculates the settling time on the basis of the history of the changes in the output voltages at the time when the sampling times reach the preset value or when changes in the output voltage of the hold capacitor reach a prescribed value or lower. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010282084(A) 申请公布日期 2010.12.16
申请号 JP20090136294 申请日期 2009.06.05
申请人 HITACHI INFORMATION & COMMUNICATION ENGINEERING LTD 发明人 YAMAMOTO TAKAHISA;YOSHINO RYOZO
分类号 G03F7/20;G01R13/34;G01R31/316;H01L21/027 主分类号 G03F7/20
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